IJRE – Volume 4 Issue 2 Paper 3

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LOW POWER AND HIGH SPEED CLOCK DISTRIBUTION USING COARSE-GRAIN POWER GATING TECHNIQUE FOR CLOCK PAIR SHARED FLIP FLOP

Author’s Name :  Mohan R | Abirami M

Volume 04 Issue 02  Year 2017  ISSN No:  2349-252X  Page no: 11-15

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Abstract:

The power savings is maximized by creating a high-fanout physically or electrically symmetric distribution that feeds many CM flip-flop (FF) receivers. Logic signals the FF receivers retain VM compatibility with low-power CMOS logic in the remainder of the chip. This paper presents the first true CM CDN and a new CM pulsed D-type FF where the clock (CLK) input is a CM receiver and the data input (D), an active low enable ,and output (Q) are VM.A new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks. Transistor-based power-gating is implemented by placing sleep transistors in-line between the circuit and the power network or the ground network.

Key Words:

Clock distribution network, cross talk, current-mode, flip-flop, low-power, power gating

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