POWER EFFICIENT TECHNIQUE FOR THE REMOVAL OF SOFT ERRORS IN MEMORIES

Author’s Name : Bautista | Pompili

Volume 01 Issue 01  Year 2014  ISSN No:  2349-252X  Page no: 6-11

Abstract -Soft errors play a serious role in memory blocks. as a result of the high proportion of transient error rate in logic circuits, the encoder and decoder electronic equipment round the memory blocks area unit additional vulnerable to soft errors and therefore should be protected. thus to safeguard encoder and decoder electronic equipment against transient errors, error-detection methodology for difference-set cyclic codes with majority logic decryption was introduced. it’s an acceptable technique to sight error however has giant decryption time and enormous access time. the same category of geometry tenuity check (EG-LDPC) codes that area unit one step Majority Logic decryption methodology is employed to scale back the decryption time. during this paper, Majority Logic Detector/Decoder is employed to any scale back the decryption time. Simulations area unit dole out and therefore the results area unit compared with the one step Majority Logic Decoder. Majority Logic Detector/Decoder is found to own less decryption time compared to Majority Logic Decoder.

Keywords –Error correction codes (ECC), Euclidean Geometry Low Density Parity Check (EG-LDPC) codes, Majority Logic Decoding (MLD) and Difference-Set Low Density Parity Check (DS-LDPC) codes