A SURVEY ON FLOORPLAN REPRESENTATIONS IN VLSI

Author’s Name : Soumya Pratik Saha | Satrajit Ghosh

Volume 02 Issue 04  Year 2015  ISSN No:  2349-3828  Page no: 23-26

Abstract – In the state of the art of computer designing interconnection of a huge number of circuit elements in a small enough area possess a challenge for the designers. This is possible if the task is divided into smaller independent modules. This is helpful for concurrent design of the individual modules as well. Interestingly the suitable placement and proper interconnection of these modules became an issue in this design. Right placement of the modules is an interesting study that needs to explore the computational aspects of geometrical shapes and appropriate graph theoretical representation. This is helpful for the automation of Floorplan and placement methods and useful in efficient realization of a huge circuit. Efficient representation of Floorplan is an interesting open problem and over few decades many researchers work on this problem to get optimal solution in terms of space and time. This work covers various representational approaches of Floorplan which should be beneficial for junior researchers, wants to start working on this area.

Keywords –Floorplan; Sliceable Floorplan; Floorplan Representation; Non-sliceable Floorplan; Mosaic Floorplan; Binary tree; v-h tree; B* tree; O tree; Twin Binary tree