IJRE – Volume 3 Issue 2 Paper 2

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DYNAMIC OVERDRIVING CURRENT MODE SIGNALING FOR ON-CHIP INTERCONNECTS TO REDUCE POWER DELAY AND AREA

Author’s Name :  Nanicka.J | Niveda .S  | Priyanka.M.G | Nithiya Devi.G

Volume 03 Issue 01  Year 2016  ISSN No:  2349-252X  Page no: 4-9

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Abstract:

An efficient scheme for low power high-speed communication over long on chip interconnects is Current-mode signaling (CMS) with dynamic overdriving technique. The Existing Scheme of Driver Pre-emphasis technique using Current Mode Signaling scheme with Feedback is implemented. CMS-Fb improves speed and reduces dynamic power consumption. Although it consumes static power, there exists a direct tradeoff between delay and static power. The proposed CMS scheme is fabricated in 180-nm CMOS technology. The CMS – smart bias scheme eliminate the Feedback and employs the corner aware bias and ring oscillator as delay element. CMS-Smart bias reduces the power consumption but increases the delay. CMS-Active bias scheme further reduces the area , power and delay by replacing the delay element and Bias circuit. Dynamic over-driving with CMS – Active bias is adopted for variation analysis which improves the area, power, delay, energy and EDP value over voltage mode signaling scheme. Delay measurement Scheme is an eminent application designed to prove the efficiency of CMS -Active bias circuit using dynamic overdriving technique.

Keywords

Current Mode Signaling, Dynamic overdriving, Active bias, On-chip Global Interconnects, D-latch, Buffer and Voltage Divider.

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