IJRE – Volume 3 Issue 2 Paper 3

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DESIGN OF LOW POWER WITH EFFICIENT RTPG FOR BIST WITH REDUCING SWITCHING ACTIVITY

Author’s Name : S.Deepika | P.Krithiga | M.Manjula | V.Pavithra | V.Naganandhini

Volume 03 Issue 01  Year 2016  ISSN No:  2349-252X  Page no: 10-13

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Abstract:

A low power (LP) programmable generator proficient of producing random test patterns with desired toggling levels compared with the built-in-self test (BIST) based linear feedback shift register. The device to produce binary sequences with preselected toggling (PRESTO) activity is allowed by test coverage improvement is embraced of a linear finite state machine (RTPG-random test pattern generator). An LP test compression method using design for testability based on scan and automatic test pattern generation were advanced to test all gate and path in a strategy. This technique creating high-quality vector for manufacturing test ,with good test coverage. This method gives a high quality test by achieving three modes such as less repetition mode, test vector coverage, switching activity. Experimental results obtained for industrial design illustrate the possibility of the proposed test schemes and are reported herein.

Keywords

Built-in self-test (BIST) , low-power(LP) test, Random test pattern generators(RTPGs),test data volume compression.

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