IJRE – Volume 3 Issue 2 Paper 5

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IMPLEMENTATION OF QUATERNARY LOGIC USING CLOCK BOOSTING TECHNIQUE FOR COMBINATIONAL CIRCUIT

Author’s Name : R. Mohan raj |B. MaheshKumar | C. KrishnaKumar | T. Mani

Volume 03 Issue 01  Year 2016  ISSN No:  2349-252X  Page no: 17-21

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Abstract:

CMOS (Complementary Metal- Oxide Semiconductor) is a class of integrated circuit in which the term ‘complementary’ refers to the fact, of typical design style with CMOS using p type and n type metal oxide semiconductor field effect transistors for logic functions. CMOS technology is employed in microprocessor, microcontroller, static RAM and other digital logic circuits. Two major characteristics of CMOS device are high noise immunity and low static power consumption. Interconnections play an important role in delay, power and area. Hence interconnection reduction is a major concern in system integration, because it increases the area, power and delay. In this project, Quaternary lookup table and clock boosting techniques are used. The clock boosting technique is to optimize the resistance and power consumption. We design a combinational circuit using the tanner and micro wind software, simulated in a standard 120nm CMOS technology, which is able to function at 120MHz consuming 120µW. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design.

Keywords:

full subtractor, vigor, area

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