IJRE – Volume 3 Issue 3 Paper 1

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DESIGN OF RADIX 4 FIR FILTER USING BOOTH MULTIPLIER FOR REDUCED POWER CONSUMPTION

Author’s Name :  Ajin Raj.D.R | Sandeep . P |Varatharaj M 

Volume 03 Issue 01  Year 2016  ISSN No:  2349-252X  Page no: 1-5

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Abstract:

Finite impulse response (FIR) filter designs mainly aims on either low area-cost or high speed or reduced power consumption. Finite Impulse Response filters are the most important element in signal processing and communication. FIR filter architecture has multiplier, adder and delay unit. So FIR filter performance is mainly based on multiplier. FIR filter using modified booth multiplier is used to reduce the power consumption and delay time in the circuit. Booth multiplier uses multilevel conditional probability (MLCP) by reducing the simulation time and easily adjusts the accuracy based on mathematical derivations. FIR filter is realized using direct form by which the area can be minimized in the circuit compared to transposed form. FIR filter is designed by using booth multiplier is implemented by HDL coding and synthesis in Xilinx tool.

Keywords:

FIR Filter, Direct form, Booth Multiplier, Multilevel Conditional probability

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