IJRE – Volume 4 Issue 1 Paper 2

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REDUCED LEAKAGE CURRENT USING DOMINO TECHNIQUES

Author’s Name :  Latha P | Suganya S | Naveenkumar R | Arivoli S

Volume 04 Issue 01  Year 2017  ISSN No:  2349-252X  Page no: 6-9

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Abstract:

As the aspect ratio of the devices shrinks down, the power supply voltage should be shortened to meet low power requirements, and the threshold voltage should also be reduced to achieve high performance. This however leads to aggressive increase in leakage current; hence the circuit’s reliability is also affected. A new domino circuit is suggested with reduced power and lower leakage for wide fan-in gates. The main intention was to make domino circuits more potent and with lower leakage and without dramatic speed degradation. The technique employed in this paper is that, the pull-up network’s mirrored current is compared with its worst case leakage current and it downturns the upper and lower boundary of the voltage swing on the dynamic node. The parasitic capacitance on the dynamic node and the keeper size for very large fan-in gates is also decreased by the expected circuit and hence the circuit can be used as a small keeper for wide fan-in gates to implement fast and robust circuits. The footer transistor is also used to shorten the leakage current. Simulation results of wide fan-in gates are build using Tanner in 16-nm technology.

Keywords:

Domino logic,Leakage-tolerant, Voltage Swing, Wide fan-in

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