SURVEY ON SCHEMES FOR FAULT TOLERANCE OF PARALLEL FILTERS
Author’s Name : Elizabeth Mathew |Abhaya Vikraman
Volume 04 Issue 01 Year 2017 ISSN No: 2349-252X Page no: 10-13
Abstract:
Maintaining high reliability in fault detection is a prominent concern in case of life critical missions. Digital filters are widely used in signal processing and communication systems like Electro Cardio Graph Signal Processors and in unmanned space missions. As the complexity of communications and signal processing systems increases, so does the number of blocks or elements that they have. The increase in complexity also poses reliability challenges and creates the need for fault-tolerant implementations. This paper proposes an efficient coding scheme for making the digital FIR filters fault tolerant and to improve the performance of the filters. Fault tolerance requires hardware redundancy and all the existing techniques uses redundant modules for that. In this technique the hardware utilization of the existing technique is minimized. Our proposed model is area efficient as it reduces the number of redundant modules used for error detection and error correction. For any number of filters number of redundant modules would be the least in this system.
Keywords:
Algorithm Based Fault Tolerance, Algorithmic Soft Error Tolerance, Single Event Effects, FIR filter
References:
- Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao,Jing Wang, and Juan Antonio Maestro “Fault Tolerant Parallel Filters Based on Error Correction Codes” IEEE Transactions on Very Large Scale Integration (VLSI) systems, February 23, 2015.
- Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao,Jing Wang, and Juan Antonio Maestro “Efficient Coding Scheme For Fault Tolerant Parallel Filters” IEEE Transactions on Circuits and Systems II, July 23, 2015.
- Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao,Jing Wang, and Juan Antonio Maestro “Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks” IEEE Transactions on Very Large Scale Integration (VLSI) systems, February 26, 2015.
- A. Reddy and P. Banarjee “Algorithm-based fault detection for signal processing applications,” IEEE Trans. Comput., vol. 39, no. 10,pp. 1304–1308, Oct. 1990.
- B. Shim and N. Shanbhag, “Energy-efficient soft error-tolerant digital signal processing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 336–348, Apr. 2006.
- T. Hitana and A. K. Deb, “Bridging concurrent and non-concurrent error detection in FIR FFT’s,” in Proc. Norchip Conf., 2004, pp. 75–78.
- Y.-H. Huang, “High-efficiency soft-error-tolerant digital signal processing using fine-grain subword-detection processing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 291–304, Feb. 2010.
- S. Pontarelli, G. C. Cardarilli, M. Re, and A. Salsano, “Totally fault tolerant RNS based FIR FFT’s,” in Proc. IEEE IOLTS, Jul. 2008, pp. 192–194.
- Z. Gao, W. Yang, X. Chen, M. Zhao, and J. Wang, “Fault missing rate analysis of the arithmetic residue codes based fault-tolerant FIR filter design,” in Proc. IEEE IOLTS, Jun. 2012, pp. 130–133.
- P. Reviriego, C. J. Bleakley, and J. A. Maestro, “Strutural DMR: A technique for implementation of soft-error tolerant FIR FFT’s,” IEEE Trans. Circuits Syst., Exp. Briefs, vol. 58, no. 8, pp. 512–516, Aug. 2011.
- P. P. Vaidyanathan. Multirate Systems and Filter Banks. Upper Saddle River, NJ, USA: Prentice-Hall, 1993.
- A. Sibille, C. Oestges, and A. Zanella, MIMO: From Theory to Implementation. San Francisco, CA, USA: Academic Press, 2010. Dept Of ECE
- P. Reviriego, S. Pontarelli, C. Bleakley, and J. A. Maestro, “Area efficient concurrent error detection and correction for parallel FFT’s,”IET Electron. Lett., vol. 48, no. 20, pp. 1258–1260, Sep. 2012.
- A. V. Oppenheim and R. W. Schafer, Discrete Time Signal Processing. Upper Saddle River, NJ, USA: Prentice-Hall 1999.
- S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall. 2004.