HIGH SPEED CLOCK SYNTHESIS WITH LOW POWER CURRENT MODE DOUBLE EDGE TRIGGERED FLIP FLOP

Author’s Name :  M Anitha Pakiyaraj | K Nantha Kumar | M Maha Lakshmi | C Nathiya | S Renuga | S VeeraVadivu

Volume 05 Issue 03  Year 2018  ISSN No:  2349-252X  Page no: 13 -15

 

 

 

Abstract:

Most of the present day systems are fully based on clocks. In a high performance Very Large Scale Integrated Circuit (VLSI) design the Clock Distribution Network (CDN) consumes a significant amount of power. New circuit approaches Current Mode (CM) logic which saves significant amount power and has less complexity compared to Voltage Mode (VM) circuit. This CM scheme uses a low power Single Edge Triggered Flip-Flop (SETFF) combined with current pulse generator that is called CMSETFF provide one-to-many signalling which is very useful for CDN. Hence this CM CDN can reduce significant amount of power when compared to VM CDN. To improve the overall Speed of CDN from existing method of CMSETFF, the proposed method uses CMDETFF. Hence the delay of proposed CMDETFF is 50% very low when compared to CMSETFF so that the speed of CDN has been increased with low power.

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