IJRE – Volume 5 Issue 4 Paper 2

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CLOCK POWER MITIGATION OF MULTI-BIT FLIP-FLOPS USING MERGING TECHNIQUE

Author’s Name :  T Bhuvaneswari | C Prema

Volume 05 Issue 04  Year 2018  ISSN No:  2349-252X  Page no: 4 – 8

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Abstract:

In modern VLSI design power has been become a burning issue. Reducing power consumption in design it enables better and cheaper products to be designed and power-related chip failures to be minimized. The power consumed by clocking gradually takes a dominant part. Multi-bit flip-flop is an effective method for clock power consumption reduction. The underlying idea behind multi-bit flip-flop method is to eliminate the total inverter number by sharing the inverters in the flip-flops. To deal with the difficulty efficiently, we have proposed several techniques. First, we perform a co-ordinate transformation to identify those flip-flops that can be merged and their legal regions. Besides, we show how to build a combination table to enumerate possible combinations of flip-flops provided by a library. Finally, we use a hierarchical way to merge flip-flops. The time complexity of our algorithm is (n1.12) less than the empirical complexity of (n2).Our algorithm significantly reduces clock power by 20–30% and the running time is very short. In the largest test case, which contains 1 700 000 flip-flops, our algorithm only takes about 5 min to replace flip-flops and the power reduction can achieve 21%.

Keywords:

VLSI,CMOS,SOC

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